The present invention relates to a semiconductor devices. Specifically, the present invention relates to a semiconductor devices including MOSFET""s that exhibit a high breakdown voltage and used in power IC""s.
Recently, so-called trench MOSFET""s, which include a gate electrode buried in a trench so that a channel may be formed along the side wall of the trench, have been developed. The trench MOSFET is advantageous to reduce the cell pitch and the on-resistance per a unit area. Although some trench lateral MOSFET structures for power IC""s have been proposed or reported, the proposed or reported trench lateral MOSFET""s have not been used practically for power IC""s yet.
The proposed trench lateral MOSFET""s include a top-drain-trench RESURF (reduced surface electric field) DMOS transistor, which includes a trench formed between a source and a drain and a gate formed in the trench (cf. Japanese Unexamined Laid Open Patent Application H06-97450). Another proposed trench gate structure includes a polysilicon gate electrode buried in a trench in the same way as the top-drain-trench RESURF DMOS transistor described above (cf. ISPSD"" 2000, pp. 47-50).
A lateral power transistor reported includes a source, a drain and a trench formed in the surface portion of a substrate, and a gate formed on the surface of the region between the source and the trench, therein a channel is formed (cf. Japanese Unexamined Laid Open Patent Application H07-74352).
The present inventors have proposed a transistor including a trench dug from the surface of an offset drain region, an insulator or a semi-insulator filling the trench and a gate electrode extended above the trench (cf. Japanese Unexamined Laid Open Patent Application H08-97411).
For manufacturing the transistor disclosed in Japanese Unexamined Laid Open Patent Application H06-97450, it is necessary to form an oxide layer, the thickness thereof is nonuniform, by selectively oxidizing an oxide film formed on the inner walls of a trench, to form a gate oxide film by wet-etching the thin portion of the nonuniform oxide layer, and to fill the trench with a polysilicon gate electrode. Therefore, the manufacturing process for manufacturing the transistor disclosed in Japanese Unexamined Laid Open Patent Application H06-97450 is complicated and includes too many steps.
The breakdown voltage of the trench gate transistor having the trench gate structure reported in ISPSD"" 2000 is not higher than 20 V to reduce the channel resistance. The trench gate structure reported in ISPSD"" 2000 is not adequate to obtain a transistor exhibiting a breakdown voltage of the several hundreds volt class, since any field plate effect is not obtained by the source electrode and the drain electrode thereof as the top plan view thereof shown in FIG. 1 of the above described report indicates.
The structure disclosed in Japanese Unexamined Laid Open Patent Application H07-74352 is not adequate to obtain a transistor exhibiting a breakdown voltage of 200 V or higher, since any field plate effect is not obtained by the source electrode and the drain electrode thereof as the structure shown in FIG. 2 of the above described patent publication indicates.
The gate electrode extended above the trench in the transistor disclosed in Japanese Unexamined Laid Open Patent Application H08-97411 is expected to exhibit a field plate effect. However, the transistor disclosed in Japanese Unexamined Laid Open Patent Application H08-97411 is not adequate to obtain a breakdown voltage of 200 V or higher, since any field plate effect is not obtained by the source electrode and the drain electrode thereof as the structure shown in FIG. 1 of the above described patent publication indicates.
In view of the foregoing, it would be desirable to provide a semiconductor device structure, which facilitates improving the breakdown voltages in the edge portions of the source and the drain by relaxing the electric field localization to the edge portions of the source and the drain, obtaining a breakdown voltage of several hundreds V, easy manufacture thereof without adding many manufacturing steps, and including trench lateral MOSFET""s exhibiting a high breakdown voltage.
According to a first aspect of the invention, there is provided a semiconductor device including: a semiconductor substrate of a first conductivity type; unit devices in the surface portion of the semiconductor substrate; each of the unit devices including: an oblong trench dug from the surface of the substrate; an oblong source region of a second conductivity type in the surface portion of the semiconductor substrate, the source region being spaced apart from the trench; an offset drain region of the second conductivity type formed along the surface of the substrate spaced apart from the source region, along the side wall of the trench and along the bottom wall of the trench; an oxide filling the trench; an oblong drain region of the second conductivity type in the surface portion of the semiconductor substrate facing to the source region across the trench; a gate insulation film on the surface portion of the semiconductor substrate between the source region and the offset drain region; a gate electrode on the gate insulation film; a source electrode connected electrically to the source region; a drain electrode connected electrically to the drain region; the direction along the long edge portion of the drain region in the planar layout of the semiconductor device being defined as a y-direction; the direction perpendicular to the x-direction in the planar layout of the semiconductor device being defined as an x-direction; the trench being extended in the y-direction from the short edge portions, extending in the x-direction, of the drain region; and the short edge portions, extending in the x-direction, of the drain region being surrounded by the offset drain region. The unit device having the structure described above is a trench lateral MOSFET exhibiting a high breakdown voltage of several hundred volts (V).
Advantageously, the length of the offset drain region in the y-direction between the edge portion, extending in the x-direction, of the trench and the short edge portion, extending in the x-direction, of the drain region is longer than the length of the offset drain region in the x-direction between an adjacent pair of the trench in the planar layout of the semiconductor device.
Advantageously, the semiconductor device further includes a base region of the first conductivity type formed in the surface portion of the semiconductor substrate, and the base region surrounds the source region formed therein and the offset drain region in the planar layout of the semiconductor device.
According to a second aspect of the invention, there is provided a semiconductor device including: a semiconductor substrate of a first conductivity type; unit devices in the surface portion of the semiconductor substrate; each of the unit devices including: a trench dug from the surface of the substrate, the trench being shaped with a ring, the trench being shared by a pair of the unit devices; a source region of a second conductivity type in the surface portion of the semiconductor substrate, the source region surrounding the trench, the source region being spaced apart from the trench; an offset drain region of the second conductivity type formed along the surface of the substrate spaced apart from the source region, along the side wall of the trench and along the bottom wall of the trench; an oxide filling the trench; a drain region of the second conductivity type in the surface portion of the semiconductor substrate facing to the source region across the trench and surrounded by the trench; a gate insulation film on the surface portion of the semiconductor substrate between the source region and the offset drain region; a gate electrode on the gate insulation film; a source electrode connected electrically to the source region; and a drain electrode connected electrically to the drain region. The unit device having the structure described above is a trench lateral MOSFET exhibiting a high breakdown voltage of several hundreds V.
Advantageously, the direction along the long edge portion of the drain region in the planar layout of the semiconductor device is defined as a y-direction; the direction perpendicular to the x-direction in the planar layout of the semiconductor device is defined as an x-direction; and the trench is wider in the y-direction than in the x-direction.
Advantageously, the direction along the long edge portion of the drain region in the planar layout of the semiconductor device is defined as a y-direction; the direction perpendicular to the y-direction in the planar layout of the semiconductor device is defined as an x-direction; and the offset drain region is formed between the drain region and the trench in the y-direction in the planar layout of the semiconductor device.
Advantageously, the length of the offset drain region between the drain region and the gate electrode is longer in the y-direction than in the x-direction.
Advantageously, the semiconductor device further includes a base region of the first conductivity type formed in the surface portion of the semiconductor substrate, and the base region surrounds the source region formed therein.
The structures described above facilitates securing a sufficient offset drain length in the y-direction and relaxing the electric field localization to the edge portion, extending in the x-direction, of the drain region.
Advantageously, the base region includes an oblong branch extended in the y-direction between the adjacent source regions of adjacent pairs of the unit devices; the edge portion, extending in the x-direction, of the distal end of the branch and the inner short edge portions, extending in the x-direction, of the adjacent gate electrodes of the adjacent pairs of the unit devices are surrounded by the offset drain region in the planar layout of the semiconductor device.
Since the electric field localization to the edge portion, extending in the x-direction, of the source region is relaxed and the potential of the region below the portion of the drain electrode, thereto a bonding wire is bonded, is kept at the drain potential, the electric field applied to the interlayer insulation film is relaxed.